1. Field of the Invention
The present invention is directed to delay circuits and, more particularly, to delay circuits that are implemented in integrated circuits that are fabricated with reduced feature-size technologies, wherein the delay circuits compensate for process, supply-voltage and/or temperature variations that could otherwise affect the integrated circuits.
2. Background Art
Integrated circuits are fabricated using reduced feature-size technologies, which have significant variations in device characteristics across the process, supply-voltage and temperature (PVT) comers. PVT variations can lead to reduced rise and/or fall times. Reduced rise and/or fall times tend to appear as unexpected delay because the signals do not reach their intended level until later than expected. For extracting maximum benefit from a given process technology, among other things, the delay across various paths of the circuit has to be controlled such that the delay variation across PVT is minimal.
Methods and systems are needed for controlling delay caused by PVT variations.
The present invention is directed to methods and systems that enable control of delay, relatively independent of process, supply-voltage and/or temperature (xe2x80x9cPVTxe2x80x9d) variations. This is made possible by, for example, sensing the output signal after a pre-determined number of inverters and adjusting the gate drive of transistors in the delay path to compensate for PVT variations.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.